Conventionally, current mirror circuits composed of MOS transistors are typically cascade connected to improve precision in the output current of the current mirror circuits.
For example, referring to the current mirror circuit section 104 shown in FIG. 8, in a first stage current mirror circuit, the gates of Pch MOS transistors P101 and P102 are connected to each other, and also to the drain of an MOS transistor P101. While a power source voltage V.sub.cc is applied to the sources of the two MOS transistors P101 and P102, the drains thereof are connected to the respective sources of MOS transistors P103 and P104 that constitute a next stage current mirror circuit.
In addition, the gates of the two MOS transistors P103 and P104 are connected to each other, and further connected to the drain of the MOS transistor P103 that serves as a current input terminal T105. Thus, as a predetermined current I.sub.in is supplied from a current source 105 via the current input terminal T105, the current mirror circuit section 104 is capable of producing an output current I.sub.out, of the same value as the current I.sub.in, flowing via the drain of the MOS transistor P104 which serves as a current output terminal T106.
In the arrangement above, since the two current mirror circuits are cascade connected, the drain potentials of the MOS transistors P101 and P102 are both equal to the sum of the gate potential of the MOS transistors P103 and P104 and a threshold voltage V.sub.th, and are thereby equal to each other. As a result, current fluctuations caused by Early effect are restrained, and the precision of the output current I.sub.out can be improved.
Nevertheless, in the current mirror circuit section 104 in the arrangement, so as to allow each current mirror circuit to operate in the saturation region thereof, the gate-drain voltages of the MOS transistors P101 to P104 need to be held at a value not less than the threshold voltage V.sub.th. Therefore, the input and output voltage ranges of the current mirror circuit section 104 are limited from GND to V.sub.cc -2V.sub.th, where V.sub.cc is the power source voltage and GND is the ground level. Cascade connection narrows down the operating voltage range in this manner, which is an obstacle in lowering the voltage of the power source.
In order to widen the operating voltage range while maintaining the output precision of the current mirror circuit, Japanese Laid-Open Patent Application No. 6-104762/1994 (Tokukaihei 6-104762) and other documents disclose a current mirror circuit section 104a to which a bias voltage power source 106 is provided as shown in FIG. 9, for example. Pch MOS transistors P111 and P112 of which the gates are connected to each other, as well as Pch MOS transistors P113 and P114 of which the gates are connected to each other, are provided to the current mirror circuit section 104a, and the drain of the MOS transistor P113 is connected to the gates of the MOS transistors P111 and P112. Meanwhile, the gates of the MOS transistors P113 and P114 are both connected to the bias voltage power source 106 so that the MOS transistors P111 to P114 are fed with a voltage that allows the MOS transistors P111 to P114 to operate in the saturation regions thereof.
Note that, similarly to the case of the current mirror circuit section 104 shown in FIG. 8, the power source voltage V.sub.cc is applied to the sources of the two MOS transistors P111 and P112; the drain of the MOS transistor P111 is connected to the source of the MOS transistor P113; and the drain of the MOS transistor P112 is connected to the source of the MOS transistor P114.
In the preceding arrangement, since the gate of the MOS transistor P111 is connected to the drain of the MOS transistor P113, the input voltage range of the current mirror circuit section 104a is from GND to V.sub.cc -V.sub.th, thereby having become wider than that of the current mirror circuit section 104 shown in FIG. 8 by a value equivalent to the threshold voltage V.sub.th. In addition, since the gate voltages of the two MOS transistors P113 and P114 are adjusted by the bias voltage power source 106 so that the MOS transistors P111 to P114 operate in the saturation regions thereof, the source voltages of the two MOS transistors P113 and P114, i.e., the drain voltages of the two MOS transistors P111 and P112, become equal to each other. As a result, the source-drain voltage Vds of the two MOS transistors P111 and P112 become equal to each other. Therefore, the precision of the output current I.sub.out can be relatively improved compared to use of a single current mirror circuit.
However, in the current mirror circuit section 104a having such an arrangement, if a variation in a property occurring during manufacture results in a difference (offset) in the gate lengths of the MOS transistors P111 and P112, the offset degrades the precision of the output current I.sub.out.
More specifically, when the current mirror circuit section 104a is manufactured, non-uniformity occurring during wafer manufacturing causes in many cases differences in properties of the two MOS transistors P111 and P112. Especially, for example, if there occurs a difference in threshold voltage V.sub.th due to a difference in gate length, one of the two MOS transistors P111 and P112, which has a higher threshold voltage V.sub.th than the other, will generate a smaller current, and there occurs a difference between the input current I.sub.in, and the output current I.sub.out.
Here, if the gate lengths of the two MOS transistors P111 and P112 are specified to a large value, adverse effects of the offset can be reduced. Nevertheless, in such a case, the gate parasitic capacity of the two MOS transistors P111 and P112 increases. As a result, a new problem arises where feeding of the output current I.sub.out does not immediately takes place when the input current I.sub.in is introduced.
More specifically, when the input current I.sub.in is in an off state, the MOS transistors P111 to P114 are also maintained in an off state. Here, when the input current I.sub.in starts flowing, electric charges stored in the gate parasitic capacity of the two MOS transistors P111 and P112 are discharged, which reduces the gate voltage. Once a point is reached where the gate-source voltage V.sub.gs exceeds the threshold voltage V.sub.th (when the condition, V.sub.gs &gt;V.sub.th, is satisfied), the two MOS transistors P111 and P112 conduct, and the output current I.sub.out changes into an on state. Here, since the gate lengths are specified to a large value to reduce the adverse effects of the offset, the gate parasitic capacity also has a large value. Therefore, feeding of the output current I.sub.out does not immediately takes place when the input current I.sub.in is introduced. As an example, if the gate parasitic capacity of the two MOS transistors P111 and P112 is 5 [pF], as shown in FIG. 10, feeding of the output current I.sub.out takes place about 1 [.mu.s] after the input current I.sub.in of 5 [.mu.A] is introduced.
Note that in a non-cascade-connected single current mirror circuit, the adverse effects of the offset of the two MOS transistors can be restrained by applying the power source voltage V.sub.cc to the sources of the two MOS transistors via resistors of the same resistance value. Nevertheless, in the conventional current mirror circuit section 104a shown in FIG. 9, if resistors are connected to the sources of the MOS transistors P111 and P112, since the voltage drop across the resistor varies depending on the input current I.sub.in, the source voltages of the MOS transistors P111 to P114 fluctuates depending on the input current I.sub.in. As a result, the gate voltages of the MOS transistors P113 and P114 need to be either increased or reduced through control of the bias voltage power source 106 according to the input current I.sub.in, so as to allow the MOS transistors P111 to P114 to operate in the saturation regions.
Note that if the gate voltage is fixed, and the input current I.sub.in is small, since the gate voltage of the MOS transistor P111 increases, the gate voltages of the MOS transistors P113 and P114 also increase, which prohibits the MOS transistors P113 and P114 to operate in the saturation regions thereof. In addition, if the input current I.sub.in further decreases, and the drain voltage of the MOS transistor P113 increases, since the source voltage of the MOS transistor P113, i.e., the drain voltage of the MOS transistor P111, increases, the two MOS transistors P111 and P112 lose current balance due to Early effect. In such a state, since the currents flowing through the two MOS transistors P111 and P112 are varied by a small fluctuation in the drain-source voltage V.sub.ds thereof, the precision of the output currents I.sub.out of the two MOS transistors P111 and P112 are greatly degraded. As a result, if the aforementioned resistors are to be interposed in the arrangement shown in FIG. 9, the gate voltage needs to be controlled through control of the bias voltage power source 106 depending upon the input current I.sub.in, which results in a complex circuit arrangement.